The mission of CAIST is to bring together a critical mass of intellectual capital and state-of-the-art infrastructure to implement a multi-phased basic science strategy to address medium range computer chip challenges.
Interconnect scaling is one of the key enablers for the continuation of the aggressive pace for increasing the functionality of chips, known as Moore's Law, beyond 2011. As part of the NY CAIST program, 27 research projects are aimed at extending copper and low-k dielectric scaling that will ultimately serve chipmakers and end-users for communications, computing, gaming, automotive and consumer electronics, and a wide range of other applications that are dependent on silicon's performance.
Every year, through the industry's collective efforts, switching speeds on chips have grown nearly 20 percent faster with a 30 percent wire and transistor density increase. However, the ability to continue this pace will eventually slow down without implementation of new interconnect materials, processes, metrology and concepts.
To accomplish the research, SRC and the NY CAIST at CNSE are directing cross-functional collaboration of researchers under one roof for coordination of projects in the following areas:
- Reduction of the sidewall and grain boundary scattering to decrease copper (Cu) resistivity at sub-40nm dimensions,
- Development of a new class of Cu diffusion barriers with thicknesses of a few atoms,
- Development of metrology to measure buried interfaces with atomic resolution,
- Optimization of the size and structure of voids in low-k dielectrics on the scale of a few atoms to increase speed while maintaining strength,
- Understanding the fundamental failure mechanisms in interconnects to reduce shorts in the dielectrics and opens in the Cu wires.