About Us > Faculty & Staff > Technical Staff > Jamal A. Qureshi

Wafer Thinning & Handling Engineer

jqureshi@albany.edu

Professional Background:

• Wafer Thinning & Handling Engineer, College of Nanoscale Science and Engineering, State University of New York at Albany, Albany, NY (2009-Present)
• Process Engineer, College of Nanoscale Science and Engineering, State University of New York at Albany, Albany, NY (2006-2009)
• Process/Equipment Support Specialist, College of Nanoscale Science and Engineering, State University of New York at Albany, Albany, NY (2005-2006)

Education:

• MBA (New Venture Development), University at Albany, SUNY, NY, 2010
• M.S. (Electrical Engineering), University of Arkansas, Fayetteville, AR, 2004
• B.S. (Electrical and Electronic Engineering), Near East University, Nicosia, Turkish Republic of Northern Cyprus, 2001

Responsibilities:

As Wafer Thinning and Handling Engineer, Mr. Qureshi is responsible for development and sustainability of wafer backgrind tool and process as well as CMP process for TSV.

Mr. Qureshi also supports 3DIC process flow and TSV integration, primarily by advanced processing and tool operation within CNSE's 300mm full-flow wafer processing facility for CNSE, SEMATECH and Center for Semiconductor Research (CSR).

Mr. Qureshi also provides technical and process support to CNSE engineering and integration for establishing and optimizing CNSE's advanced processes and to facilitate CNSE customers and joint development programs.

Technical Papers:

“A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non Bosch through-silicon-via (TSV) etch, TSV metrology and TSV integration”, Co-author (IEEE 3DIC System Integration, September 2009)

“Manufacturable 300mm wafer thinning for 3D interconnect application, Chemical Mechanical Planarization as a Semiconductor Technology Enabler”, Author (MRS 1249-E01-02, April 2010)

“High removal rate CMP process on TSV thick Cu overburden, Chemical Mechanical Planarization as a Semiconductor Technology Enabler”, Co-author (MRS 1249-E01-08, April 2010)

“An optimized 300mm BCB wafer bonding process for 3D, Materials, Processes, Integration, and Reliability in Advanced Interconnects for Micro- and Nanoelectronics”, Co-author (MRS 1249-F09-06, April 2010)