About Us > Faculty & Staff > Technical Staff > Daniel França Senior Front End Of Line (FEOL) Process Development Engineer

Professional Background:

• Process Development Engineer (FEOL), College of Nanoscale Science and Engineering (2009-present)
• Lithography Process Engineering Manager, Qimonda NA (2007-2009)
• Process Engineering & Engineering Manager Positions, IBM Microelectronics (2001-2007)

Education:

• BSE, Electrical Engineering, University of Michigan, College of Engineering, Ann Arbor, MI, 2000.

Responsibilities:

As a Process Development Engineer, Mr. França is responsible for multiple aspects of joint development activities with CNSE's ever growing corporate partnerships. Mr. França works to ensure that the partners challenging integration schemes are accomplished using novel front end of line processing solutions.

Mr. França is the primary contact for front end of line thin film depositions, epitaxial grown films and unique thermal anneals. He supports conventional planer CMOS and non-planer FinFET and Nanowire applications, with high-k gate dielectrics and channel straining films for improved performance.

Issued Patents:

• Real Time Profiling and Conditioning of Chemical Mechanical Polish Pads Patent No. 6,343,974; Date of Patent - February 5, 2002.
• Light Energy Cleaning of Polish Pads Patent No. 6,217,422; Date of Patent - April 17, 2001.
• Method and Apparatus for Ozone Generation and Surface Treatment Patent No. 6,178,973; Date of Patent - January 30, 2001.

Conference Publications and Presentations:

• A Yield Enhancement Methodology for Launching New Technologies Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium, September 13, 2005, pp. 491- 494.